As the rate of data communication increases, the network infrastructure must be able to keep pace. This requires careful design of network infrastructure devices at the architecture and circuit levels. Parallel to the increase in data rate, the network traffic has become more and more heterogenous. Each traffic type requires treatment peculiar to itself. The net effect of these two developments is that the burden on devices forming the core of network infrastructure is too much for conventionally designed devices to be able to handle the traffic. Handling traffic at a given rate depends on the speed of operation within the device. Achieving very high traffic processing rate requires custom design of key components such as memories. The purpose of this research is circuit-level design of critical components for traffic handling at rate of 12.8 terabits per second.

2021

2022