DARE SGA 1

HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware (HW) and software (SW) activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of next-generation post-exascale EU supercomputers.

2025

2028