Hardware accelerators can significantly improve energy efficiency for tasks such as AI, network processing, physics simulation, or cryptography. However, with the high pace in algorithm development, the existing fixed function accelerators quickly become chip waste. The proposed research aims to avoid chip waste and automate the generation of reusable programmable hardware accelerators using reinforcement learning methods. The methods automatically find a valid low cost accelerator design with desired properties. The methods start from high-level program descriptions and generate complete compiler programmable accelerators with desired qualities such as optimized energy-efficiency. The research is made possible by combining chip design knowledge at the Customized Parallel Computing research group at Tampere University with reinforcement learning and algorithm development knowledge at the Robot Learning research group at Aalto University.

2023

2025